Please use this identifier to cite or link to this item: http://repository.ucc.edu.co/handle/ucc/2549
Title: Static Worst-Case Execution Time Optimization using DPSO for ASIP Architecture
Author: Venkanna, Mood
Rao, Rameshwar
Keywords: Embedded Processor; ASIP; WCET; Optimization; PSO; DPSO;
Description: Introduction: Application-specific instructions improve the energy, performance, and code size of configurable processors significantly. The design of these instructions is performed by conversion of patterns related to application-specific operation into effective complex instructions research was done at ICITKM Conference,University of Delhi ,India in 2017.Methods: Static analysis is a prominent method of research during late 80s however, end-to-end measurements is a standard approach in industrial setting. Either the tools of static analysis perform at a high-level in order to determine the program structure, which works on source code, or executable disassembled binary. It is possible to work at a low-level provided the real hardware timing information for the executable task having the desired features.Results: We experimented, tested and evaluated our analysis with an H.264 encoder application that utilizes nine CIs covering the majority computation intensive kernels. Multimedia applications are frequently subject to hard real time constraints in the field of computer vision. The H.264 encoder consists of complicated control flow with more number of decisions and nested loops .The parameters evaluated were different numbers of s partitions A (300 slices each on a Xilinx Virtex 7), reconfiguration bandwidths as well as relations of CPU frequency and fabric frequency fCPU/ffabric. ffabric remains constant at 100MHz, and we select multiple values of it for fCPU that resemble realistic units. Note that while the WCET in seconds (WCET cycles/ f CPU) is anticipated to get lower (better) with higher fCPU, the WCET cycles are increasing (at a constant f fabric), because hardware CIs perform less computations on the reconfigurable fabric within one CPU cycle. Conclusions: The method is similar to the hybridization of tree and path-based methods, which are less precise and global IPET method, which is more precise. Optimization is carried with Discrete Particle Swarm Optimization (DPSO) algorithm for WCET. For several real-world applications involving embedded processor, the proposed technique develops improved instruction sets corresponding to the native instruction sets. Originality: For WCET estimation, flow analysis, low-level analysis and calculation phases of the program need to be considered. Flow analysis phase or the high-level analysis helps to extract the program’s dynamic behavior that gives information on functions being called, number of loop iteration, dependencies among if-statements, etc. As the analysis is unaware of the execution path corresponding to the longest execution time.Limitations: path is executed within a kernel iteration relies upon the nature of MB, either I-MB or P-MB, determined by the Motion Estimation kernel, that is, it is input dependent the I-MB and P-MB paths also contain separate CIs leading to instability of the worst-case path, that is, adding more partitions to the current worst-case path can result in the other path becoming the worst case. The pipeline stalls for the reconfiguration delay and continues with entering the kernel once reconfiguration finishes
Publisher: Universidad Cooperativa de Colombia
Appears in Collections:Revista Ingeniería Solidaria

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